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-- Company: 
-- Engineer: 
-- 
-- Create Date:    13:30:39 09/27/2013 
-- Design Name: 
-- Module Name:    adder_64 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity adder_64 is
	port(	a, b : in STD_LOGIC_VECTOR(63 downto 0);
			sum : out STD_LOGIC_VECTOR(63 downto 0));
end adder_64;

architecture Behavioral of adder_64 is
	component adder_32 
		 Port ( a : in  STD_LOGIC_VECTOR (31 downto 0);
				  b : in  STD_LOGIC_VECTOR (31 downto 0);
				  carryIn : in  STD_LOGIC;
				  sum : out  STD_LOGIC_VECTOR (31 downto 0);
				  carryOut : out  STD_LOGIC);
	end component;
	signal a1, b1, a2, b2, sum1, sum2 : STD_LOGIC_VECTOR(31 downto 0) := X"00000000";
	signal carryIn1, carryOut1, carryIn2, carryOut2 : STD_LOGIC := '0';
begin
	adder1 : adder_32 port map(a1, b1, carryIn1, sum1, carryOut1);
	adder2 : adder_32 port map(a2, b2, carryIn2, sum2, carryOut2);
		
	carryIn1 <= '0';
	carryIn2 <= carryOut1;
	
	a2 <= a(63 downto 32);
	a1 <= a(31 downto 0);
	
	b2 <= b(63 downto 32);
	b1 <= b(31 downto 0);
	
	sum <= sum2 & sum1;
end Behavioral;

